1. Field of the Invention
The invention relates to a technique and apparatus for storing and addressing data in the memory of a computer system and more particularly to a technique and apparatus for storing and addressing a memory in which multiple words of data are to be transferred over a multiple word wide data bus.
2. Description of the Prior Art
In most modern computer systems, the data within memory is organized into fixed length words. Each word is comprised of a fixed number of bits and is referenced by an address which indicates the word's position within the memory. In most computer systems, the memory addresses are binary encoded and are transferred to the memory on a data bus which contains as many signal lines as there are binary digits (bits) required to represent the highest word address. For example, if a memory contains 1,024 words of data, contained in addresses 0 through 1,023, the memory would be addressed by providing a binary encoded address consisting of 10 bits (1,111,111,111 binary equals 1,023 decimal which is the address of the last location in memory).
In many modern minicomputers, the data words are organized in words of 16 bits each, and each time that the memory is referenced by an address on an address bus, the memory responds by either reading a 16-bit word from memory and placing it on the data bus or takes a 16-bit word from the data bus and writes it into the addressed location in memory. The memory does a read or a write depending upon control signals appearing on a control bus.
Minicomputers have now evolved to the point where super-minicomputers are now appearing on the market. These super-minicomputers are of higher performance than the minicomputers. This higher performance of the super-minicomputers is achieved by providing faster circuits within these central processing units (CPU), by processing more data in parallel, by having faster bus transfer rates, by having faster memories, and by a variety of other techniques. Because the cost of developing software is relatively high compared to the purchase price of a super-minicomputer, manufacturers of minicomputers who have produced super-minicomputers have made the super-minicomputer software compatible with their earlier minicomputers so that software which executes on their minicomputer will also execute on their super-minicomputer.
One way of increasing the performance of a minicomputer to produce a super-minicomputer is to have the super-minicomputer process multiple words of data in parallel such that when the super-minicomputer references the memory and provides a memory address of a 16-bit data word, the memory of the super-minicomputer will retrieve or store multiple 16-bit words in parallel. For example, if the CPU of a super-minicomputer wants to read location 1,000 from memory, the CPU can place the address of location 1,000 on the address bus and the main memory will retrieve the contents of location 1,000 and location 1,001 (the next addressed location) and return the two 16-bit data words in parallel on a data bus which is 32 bits wide (twice as wide as the 16-bit data bus on the previous minicomputer).
One method of organizing the memory of a super-minicomputer so that it can retrieve multiple words in parallel is to organize the memory to have an even bank and an odd bank such that all even addressed words are contained in the even bank and all odd addressed words are contained in the odd bank. Using this organization, if location 1,000 and location 1,001 are to be read from main memory, the main memory will read the contents of location 1,000 from the even bank and the contents of location 1,001 from the odd bank and place them on the bus such that the address location is in the leftmost word on the data bus and the address location plus one is in the rightmost word of the data bus. In this example, location 1,000 from the even bank would be in the leftmost word on the data bus and the contents of location of 1,001 from the odd bank would be in the rightmost word of the data bus. However, if locations 1,001 and 1,002 are to be read from memory, location 1,001 would be read from the odd bank and placed in the leftmost word on the data bus and location 1,002 would be read from the even bank and placed in the rightmost word on the data bus. As can be seen from the above examples, in some cases the word read from the even bank appears in the leftmost word on the data bus; in the other cases, the word read from the odd bank will appear in the leftmost word on the data bus. The rule being that the addressed word always appears in the leftmost word and the addressed word plus one appears in the rightmost word on the data bus. In order to achieve this alignment of the words on a multiword wide data bus, there is usually a crossbar arrangement within the main memory to align the data as it is read from memory and placed on the data bus or to align the data as it is taking from the data bus and written into the main memory. In addition to this crossbar logic, the main memory must also have the ability to increment by one the address presented by the address bus so that it may compute the address of the second location to be read from memory.
This crossbaring of the data from or to the data bus as this information is written to or read from main memory and the incrementing of the address requires logic within the memory. The propagation time of the various signals through the address incrementing and crossbaring logic increases the memory response time.
What is needed, therefore, is a technique and apparatus for eliminating the need of crossbaring data as multiple words of data are read from memory in parallel and a means for eliminating the requirement to increment the address of the first word of multiple words of data which are to be retrieved from a memory.